1. Field of the Invention
The present invention relates to a semiconductor memory and its production process, and more particularly, the invention relates to a semiconductor memory provided with a memory transistor having a charge storage layer and a control gate, and its production process.
2. Description of Related Art
As a memory cell of an EEPROM, is known a device of a MOS transistor structure having a charge storage layer and a control gate in a gate portion, in which an electric charge is injected into and released from the charge storage layer by use of a tunnel current. In this memory cell, data “0” and “1” is stored as changes in a threshold voltage by the state of the charge in the charge storage layer. For example, in the case of an n-channel memory cell using a floating gate as the charge storage layer, when a source/drain diffusion layer and a substrate are grounded and a high positive voltage is applied to the control gate, electrons are injected from the substrate into the floating gate by a tunnel current. This injection of electrons shifts the threshold voltage of the memory cell toward positive. When the control gate is grounded and a high positive voltage is applied to the source/drain diffusion layer or the substrate, electrons are released from the floating gate to the substrate by the tunnel current. This release of electrons shifts the threshold voltage of the memory cell toward negative.
In the above-described operation, a relationship of capacity coupling between the floating gate and the control gate with capacity coupling between the floating agate and the substrate plays an important role in effective injection and release of electrons, i.e., effective writing and erasure. That is, the larger the capacity between the floating gate and the control gate, the more effectively the potential of the control gate can be transmitted to the floating gate and the easier the writing and erasure become.
With recent development in semiconductor technology, especially, in micro-patterning techniques, the size reduction and the capacity increase of memory cells of EEPROM are rapidly progressing. Accordingly, it is an important how large capacity can be ensured between the floating gate and the control gate.
For increasing the capacity between the floating gate and the control gate, it is necessary to thin a gate insulating film therebetween, to increase the dielectric constant of the gate insulating film or to enlarge an area where the floating gate opposes the control gate.
However, the thinning of the gate insulating film is limited in view of reliability of memory cells. For increasing the dielectric constant of the gate insulating film, a silicon nitride film is used as the gate insulating film instead of a silicon oxide film. This is also questionable in view of reliability and is not practical. Therefore, in order to ensure a sufficient capacity between the floating gate and the control gate, it is necessary to set a sufficient overlap area therebetween. This is, however, contradictory to the size reduction of memory cells and the capacity increase of EEPROM.
In an EEPROM disclosed by Japanese Patent No.2877462, memory transistors are formed by use of sidewalls of a plurality of pillar-form semiconductor layers arranged in matrix on a semiconductor substrate, the pillar-form semiconductor layers being separated by trenches in a lattice form. A memory transistor is composed of a drain diffusion layer formed on the top of a pillar-form semiconductor layer, a common source diffusion layer formed at the bottom of the trenches, and a charge storage layer and a control gate which are around all the periphery of the sidewall of the pillar-form semiconductor layer. The control gates are provided continuously for a plurality of pillar-form semiconductor layers lined in one direction so as to form a control gate line, and a bit line is connected to drain diffusion layers of a plurality of memory transistors lined in a direction crossing the control gate line. The charge storage layer and the control gate are formed in a lower part of the pillar-form semiconductor layer. This construction can prevent a problem in a one transistor/one cell structure, that is, if a memory cell is over-erased (a reading potential is 0 V and the threshold is negative), a cell current flows in the memory cell even if it is not selected.
With this construction, a sufficiently large capacity can be ensured between the charge storage layer and the control gate with a small area occupied. The drain regions of the memory cells connected to the bit lines are formed on the top of the pillar-form semiconductor layers and completely insulated from each other by the trenches. A device isolation region can further be decreased and the memory cells are reduced in size. Accordingly, it is possible to obtain a mass-storage EEPROM with memory cells which provide excellent writing and erasing efficiency.
The prior-art EEPROM is explained with reference to figures. FIG. 486 is a plan view of a prior-art EEPROM, and FIGS. 487(a) and 487(b) are sectional views taken on lines A-A′ and B-B′, respectively, in FIG. 486.
In FIG. 486, pillar-form silicon semiconductor layers 2 are columnar, that is, the top thereof is circular. However, the shape of the pillar-form silicon semiconductor layers need not be columnar. In the plan view of FIG. 486, selection gate lines formed by continuing gate electrodes of selection gate transistors are not shown for avoiding complexity of the figure.
In the prior art, is used a P-type silicon substrate 1, on which a plurality of pillar-form P-type silicon layers 2 are arranged in matrix. The pillar-form P-type silicon layers 2 are separated by trenches 3 in a lattice form and functions as memory cell regions. Drain diffusion layers 10 are formed on the top of the silicon layers 2, common source diffusion layers 9 are formed at the bottom of the trenches 3, and oxide films 4 are buried at the bottom of the trenches 3. Floating gates 6 are formed in a lower part of the silicon layers 2 with intervention of tunnel oxide films 5 so as to surround the silicon layers 2. Outside the floating gates 6, control gates 8 are formed with intervention of interlayer insulating films 7. Thus memory transistors are formed.
Here, as shown in FIGS. 486 and 487(b), the control gates 8 are provided continuously for a plurality of memory cells in one direction so as to form control gate lines (CG1, CG2, . . . ). Gate electrodes 32 are provided around an upper part of the silicon layers 2 with intervention of gate oxides films 31 to form the selection gate transistors, like the memory transistors. The gate electrodes 32 of the selection gate transistors, like the control gates 8 of the memory cells, are provided continuously in the same direction as that of the control gates 8 of the memory cells so as to form selection gate lines, i.e., word lines WL (WL1, WL2, . . . ).
Thus, the memory transistors and the selection gate transistors are buried in the trenches in a stacked state. The control gate lines leave end portions as contact portions 14 on the surface of silicon layers, and the selection gate lines leaves contact portions 15 on silicon layers on an end opposite to the contact portions 14 of the control gates. Al wires 13 and 16 to be control gate lines CG and the word lines WL, respectively, are contacted to the contact portion 14 and 15, respectively. At the bottom of the trenches 3, common source diffusion layers 9 of the memory cells are formed, and on the top of the silicon layers 2, drain diffusion layers 10 are formed for every memory cell. The resulting substrate with the thus formed memory cells is covered with a CVD oxide film 11, where contact holes are opened. Al wires 12 are provided which are to be bit lines BL which connects the drain diffusion layers 10 of memory cells lined in a direction crossing the word lines WL. When patterning is carried out for the control gate lines, a mask is formed of PEP on pillar-form silicon layers at an end of a cell array to leave, on the surface of the silicon layers, the contact portions 14 of a polysilicon film which connect with the control gate lines. To the contact portions 14, the Al wires 13 which are to be control gate lines are contacted by Al films formed simultaneously with the bit lines BL.
A production process for obtaining the structure shown in FIGS. 487(a) and 487(b) is explained with reference to FIGS. 488(a) to 491(g).
A P-type silicon layer 2 with a low impurity concentration is epitaxially grown on a P-type silicon substrate 1 with a high impurity concentration to give a wafer. A mask layer 21 is deposited on the wafer and a photoresist pattern 22 is formed by a known PEP process. The mask layer 21 is etched using the photoresist pattern 22 (see FIG. 488(a)).
The silicon layer 2 is etched by a reactive ion etching method using the resulting mask layer 21 to form trenches 3 in a lattice form which reach the substrate. Thereby the silicon layer 21 is separated into a plurality of pillar-form islands. A silicon oxide film 23 is deposited by a CVD method and anisotropically etched to remain on the sidewalls of the pillar-form silicon layers 2. By implantation of N-type impurity ions, drain diffusion layers 10 are formed on the top of the pillar-form silicon layers 2 and common source diffusion layers 9 are formed at the bottom of the trenches (see FIG. 488(b)).
The oxide films 23 around the pillar-form silicon layers 2 are etched away by isotropic etching. Channel ion implantation is carried out on the sidewalls of the pillar-form silicon layers 2 by use of a slant ion implantation as required. Instead of the channel ion implantation, an oxide film containing boron may be deposited by a CVD method with a view to utilizing diffusion of boron from the oxide film. A silicon oxide film 4 is deposited by a CVD method and isotropically etched to be buried at the bottom of trenches 3. Tunnel oxide films 5 are formed to a thickness of about 10 nm around the silicon layers 2 by thermal oxidation. A first-layer polysilicon film 5 is deposited and anisotropically etched to remain on lower sidewalls of the pillar-form silicon layers 2 as floating gates 6 around the silicon layers 2 (see FIG. 489(c)).
Interlayer insulating films 7 are formed on the surface of the floating gates 5 formed around the pillar-form silicon layers 2. The interlayer insulating films 7 are formed of an ONO film, for example. The ONO film is formed by oxidizing the surface of the floating gate 6 by a predetermined thickness, depositing a silicon nitride film by a plasma-CVD method and then thermal-oxidizing the surface of the silicon nitride film. A second-layer polysilicon film is deposited and anisotropically etched to form control gates 8 on lower parts of the pillar-form silicon layers 2 (see FIG. 489(d)). At this time, the control gates 8 are formed as control gate lines continuous in a longitudinal direction in FIG. 486 without need to perform a masking process by previously setting intervals between the pillar-form silicon layers 2 in the longitudinal direction at a predetermined value or less. Unnecessary parts of the interlayer insulating films 7 and underlying tunnel oxide films 2 are etched away. A silicon oxide film 111 is deposited by a CVD method and etched halfway down the trenches 3, that is, to a depth such that the floating gates 6 and control gates 8 of the memory cells are buried and hidden (see FIG. 490(e)).
A gate oxide film 31 is formed to a thickness of about 20 nm on exposed upper parts of the pillar-form silicon layers 2 by thermal oxidation. A third-layer polysilicon film is deposited and anisotropically etched to form gate electrodes 32 of MOS transistors (see FIG. 490(f)). The gate electrodes 32 are patterned to be continuous in the same direction as the control gate lines run, and form selection gate lines. The selection gate lines can be formed continuously in self-alignment, but this is more difficult than the control gates 8 of the memory cells. For, the selection gate transistors are single-layer gates while the memory transistors are two-layered gates, and therefore, the intervals between adjacent selection gates are wider than the intervals between the control gates. Accordingly, in order to ensure that the gate electrodes 32 are continuous, the gate electrodes may be formed in a two-layer polysilicon structure, a first polysilicon film may be patterned to remain only in locations to connect the gate electrodes by use of a masking process, and a second polysilicon film may be left on the sidewalls.
Masks for etching the polysilicon films are so formed that contact portions 14 and 15 of the control gate lines and the selection gate lines are formed on the top of the pillar-form silicon layers at different ends. A silicon oxide film 112 is deposited by a CVD method and, as required, is flattened. Contact holes are opened. An Al film is deposited and patterned to form Al wires 12 to be bit lines BL, Al wires 13 to be control gate lines CG and Al wires 16 to be word lines WL at the same time (see FIG. 491(g)).
FIG. 492(a) schematically shows a sectional structure of a major part of one memory cell of the prior-art EEPROM, and FIG. 492(b) shows an equivalent circuit of the memory cell. The operation of the prior-art EEPROM is briefly explained with reference to FIGS. 492(a) to 492(b).
For writing by use of injection of hot carriers, a sufficiently high positive potential is applied to a selected word line WL, and positive potentials are applied to a selected control gate line CG and a selected bit line BL. Thereby, a positive potential is transmitted to the drain of a memory transistor Qc to let a channel current flow in the memory transistor Qc and inject hot carriers. Thereby, the threshold of the memory cell is shifted toward positive. For erasure, 0 V is applied to a selected control gate CG and high positive potentials are applied to the word line WL and the bit line BL to release electrons from the floating gate to the drain. For erasing all the memory cells, a high positive potential may be applied to the common sources to release electrons to the sources. Thereby, the thresholds of the memory cells are shifted toward negative. For reading, the selection gate transistor is rendered ON by the word line WL and the reading potential is applied to the control gate line CG. The judgement of a “0” or a “1” is made from the presence or absence of a current.
In the case where an FN tunneling is utilized for injecting electrons, high potentials are applied to a selected control gate line CG and a selected word line WL and 0 V is applied to a selected bit line BL to inject electrons from the substrate to the floating gate.
This prior art provides an EEPROM which does not mis-operate even in an over-erased state thanks to the presence of the selection gate transistors.
The prior-art EEPROM does not have diffusion layers between the selection gate transistors Qs and the memory transistors Qc as shown in FIG. 492(a). For, it is hard to form the diffusion layers selectively on the sidewalls of the pillar-form silicon layers. Therefore, in the structure shown in FIGS. 487(a) and 487(b), desirably, separation oxide films between the gates of the memory transistors and the gates of the selection gate transistors are as thin as possible. In the case of utilizing the injection of hot electrons, in particular, the separation oxide films need to be about 30 to 40 nm thick for allowing a sufficient “H” level potential to be transmitted to the drain of a memory transistor. Such fine intervals cannot be practically made only by burying the oxide films by the CVD method as described above in the production process. Accordingly, desirably, the oxide films are buried in such a manner that the floating gates 6 and the control gates 8 are exposed, and thin oxide films are formed on exposed parts of the floating gates 6 and the control gates 8 simultaneously with the formation of the gate oxide films for the selection gate transistors.
Further, according to the prior art, since the pillar-form silicon layers are arranged with the bottom of the lattice-form trenches forming an isolation region and the memory cells are constructed to have the floating gates formed to surround the pillar-form silicon layers, it is possible to obtain a highly integrated EEPROM in which the area occupied by the memory cells are small. Furthermore, although the memory cells occupy a small area, the capacity between the floating gates and the control gates can be ensured to be sufficiently large.
According to the prior art, the control gates of the memory cells are formed to be continuous in one direction without using a mask. This is possible, however, only when the pillar-form silicon layers are arranged at intervals different between a longitudinal direction and a lateral direction. That is, by setting the intervals between adjacent pillar-form silicon layers in a word line direction to be smaller than the intervals between adjacent pillar-form silicon layers in a bit line direction, it is possible to obtain control gate lines that are separated in the bit line direction and are continuous in the word line direction automatically without using a mask.
In contrast, when the pillar-form silicon layers are arranged at the same intervals both in the longitudinal direction and in the lateral direction, a PEP process is required. More particularly, the second-layer polysilicon film is deposited thick, and through the PEP process to form a mask, the second-layer polysilicon film is selectively etched to remain in locations to be continuous as control gate lines. The third-layer polysilicon film is deposited and etched to remain on the sidewalls as described regarding the production process of the prior art. Even in the case where the pillar-form silicon layers are arranged at intervals different between the longitudinal direction and the lateral direction, the continuous control gate lines cannot be automatically formed depending upon the intervals of the pillar-form silicon layers. In this case, the mask process by the PEP process as described above can be used for forming the control gate lines continuous in one direction.
Although the memory cells of the prior art as described above are of a floating gate structure, the charge storage layers do not necessarily have the floating gate structure and may have a structure such that the storage of a charge is realized by a trap in a laminated insulating film, e.g., a MNOS structure.
FIG. 493 is a sectional view of a prior-art memory with memory cells of the MNOS structure, corresponding to FIG. 487(a). A laminated insulating film 24 functioning as the charge storage layer is of a laminated structure of a tunnel oxide film and a silicon nitride film, or of a tunnel oxide film, a silicon nitride film and further an oxide film formed on the silicon nitride film.
FIG. 494 is a sectional view of a prior-art memory in which the memory transistors and the selection gate transistors of the above-described prior art are exchanged, i.e., the selection gate transistors are formed in the lower parts of the pillar-form silicon layers 2 and the memory transistors are formed in the upper parts of the pillar-form silicon layers 2. FIG. 494 corresponds to FIG. 487(a). This structure in which the selection gate transistors are provided on a common source side can apply to the case where the injection of hot electrons is used for writing.
FIG. 495 shows a prior-art memory in which a plurality of memory cells are formed on one pillar-form silicon layer. Like numbers denote like components in the above-described prior-art memories and the explanation thereof is omitted.
In this memory, a selection gate transistor Qs1 is formed in the lowermost part of a pillar-form silicon layer 2, three memory transistors Qc1, Qc2 and Qc3 are laid above the selection gate transistor Qs1, and another selection gate transistor Qs2 is formed above. This structure can be obtained basically by repeating the aforesaid production process.
As described above, the prior-art techniques can provide highly integrated EEPROMs whose control gates and charge storage layers have a sufficient capacity therebetween and whose memory cells occupy a decreased area, by constructing the memory cells using memory transistors having the charge storage layers and the control gates by use of the sidewalls of the pillar-form semiconductor layers separated by the lattice-form trenches.
However, if a plurality of memory cells are connected in series on one pillar-form semiconductor layer and the thresholds of the memory cells are supposed to be the same, significant changes take place in the thresholds of memory cells at both ends of the memory cells connected in series owing to a back-bias effect of the substrate in a reading operation. In the reading operation, the reading potential is applied to the control gate lines CG and the “0” or “1” is judged from the presence of a current. For this reason, the number of memory cells connected in series is limited-in view of the performance of memories. Therefore, the production of mass-storage memories is difficult to realize.
The problem that the thresholds of memory cells are changed owing to a back-bias effect is true not only of the case where a plurality of memory cells are connected in series on one pillar-form semiconductor layer but also of the case where one memory cell is formed on one pillar-form semiconductor, depending upon variations in the back-bias effect of the substrate in an inplanar direction.
In the prior art memory, an impurity diffusion layer is not formed between memory cells on the same pillar-form semiconductor layer. However, it is preferable that an impurity diffusion layer is formed therebetween.
Furthermore, in the prior-art memories, the charge storage layers and the control gates are formed in self-alignment with the pillar-form semiconductor layers. Taking mass storage of the cell array into consideration, the pillar-form semiconductor layers are preferably formed at the minimum photoetching dimension.
In the case where the floating gates are used as the charge storage layers, the capacity coupling between the floating gates and the control gates and between the floating gates and the substrate is determined by the area of the outer periphery of the pillar-form semiconductor layers, the area of the outer periphery of the floating gate, the thickness of the tunnel oxide films insulating the floating gates from the pillar-form semiconductor layers and the thickness of the interlayer insulating films insulating the floating gates form the control gates. In the prior-art memories, the charge storage layers and the control gates are formed to surround the pillar-form semiconductor layers by utilizing the sidewalls of the pillar-form semiconductor layers in order that the capacity between the charge storage layers and the control gates is ensured to be sufficiently large. However, in the case where the pillar-form semiconductor layers are formed at the minimum photoetching dimension and the thickness of the tunnel oxide films and that of the interlayer insulating film are fixed, the capacity between the charge storage layers and the control gates is determined simply by the area of the outer periphery of the floating gates, that is, the thickness of the floating gates. Therefore, it is difficult to increase the capacity between the charge storage layers and the control gates without increasing the area occupied by the memory cells. In other words, it is difficult to increase the ratio of the capacity between the floating gates and the control gates to the capacity between the floating gates and the pillar-form semiconductor layers without increasing the area occupied by the memory cells.
Further, if transistors are formed in a direction vertical to the substrate stage by stage, there occur variations in characteristics of the memory cells owing to differences in the properties of the tunnel oxide films and differences in the profile of diffusion layers. Such differences are generated by thermal histories different stage by stage.